Title:
MEMORY MANAGEMENTION PACKET DATA MODE SYSTEM
Document Type and Number:
Japanese Patent JPH02216943
Kind Code:
A
Abstract:
PURPOSE: To improve a memory management system, and to make a CPU processing time inefficient by providing a means for generating the change of a field signal and transmitting a message end signal to a DMA controller. CONSTITUTION: Packet data are communicated to or from the storage part of a memory. Each message in a packet data mode system is provided with a control address field and a data field. This system is provided with a means 228 for generating the change of a field signal, and communicating the signal to a DMA controller 224. Moreover, this system is provided with the means 228 for generating a message end signal, and communicating the message end signal to the DMA controller 224. A control address field is stored separated from the data field. Thus, a data storage efficiency can be improved, and the density of information to be packed in the memory storage part can be improved.
Inventors:
RICHIYAADO JIIN SOUERU
ROBAATO PIITAASU
ROBAATO PIITAASU
Application Number:
JP28000289A
Publication Date:
August 29, 1990
Filing Date:
October 30, 1989
Export Citation:
Assignee:
NAT SEMICONDUCTOR CORP
International Classes:
H04L29/06; G06F13/28; H04L29/08; (IPC1-7): H04L29/06; H04L29/08
Attorney, Agent or Firm:
Kazuo Kobashi (1 person outside)