Title:
METHOD AND APPARATUS FOR TESTING STATIC RANDOM ACCESS MEMORY ARRAY
Document Type and Number:
Japanese Patent JPH05304266
Kind Code:
A
Abstract:
PURPOSE: To execute production line tests and technical tests on short circuit to detect not so serious defects of an SRAM array during the production line tests by changing applied voltages and cells to be selected. CONSTITUTION: This method enables a test mode condition, disabling word line bus transistors 20, 21 to shut off all cells from bit lines, enabling column selects transistors 27, 28 to select all columns of an array, enabling transistors 30, 31 of output lines to connect bit lines and bit 304 lines of all the array cells to test pads, disabling after a precharge cycle, transistors 22, 23 to shut off the bit lines and bit 304 lines from a pre-charging circuit, applying high-level voltages to output pads to measure currents and connecting low power voltages to the output pads to determine the array to be rejected in the test, if a current higher than a pre-selected value is measured.
Inventors:
JIEIMUZU CHIYAN
ROBAATO II RAARUSEN
SUTEIIBU ISUKIRUDOSEN
ROBAATO II RAARUSEN
SUTEIIBU ISUKIRUDOSEN
Application Number:
JP35881092A
Publication Date:
November 16, 1993
Filing Date:
December 28, 1992
Export Citation:
Assignee:
INTEL CORP
International Classes:
G01R31/28; G01R31/30; G11C29/00; G11C29/50; G11C29/56; H01L21/66; H01L27/10; (IPC1-7): H01L27/10; G01R31/318; G11C29/00; H01L21/66
Attorney, Agent or Firm:
Masaki Yamakawa
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