Title:
METHOD AND DEVICE FOR SYNCHRONIZING SIGNAL
Document Type and Number:
Japanese Patent JPH05243982
Kind Code:
A
Abstract:
PURPOSE: To provide a simple digital PLL provided with a large follow-up range and satisfactory resolution by synchronizing inner signals in relation to a reference signal having a reference period. CONSTITUTION: A digital phase comparator 10 receiving signals SYNC and Fint and supplying a signal SGN is provided. The signal Fint is obtained by dividing a clock signal CK by N in a programmable divider (DIVN) 13. A control circuit (CTRL) 18 increases or decreases the numeric value NH and the numeric value NL of memories 16 and 17 as the function of a series of states of the signal SGN. The control circuit 18 analyzes a series of the latest states of the signal SGN in a window provided with the number of periods which are previously decided, four, for example. When the phase of the inner signal advances on the phase of a synchronizing signal, the phase comparison signal of a logic state ('1') which is previously decided is provided. When it is not, the phase comparison signal of a complementary logic state ('0') is provided.
Inventors:
JIYATSUKU MEIYAA
Application Number:
JP22098792A
Publication Date:
September 21, 1993
Filing Date:
July 29, 1992
Export Citation:
Assignee:
SGS THOMSON MICROELECTRONICS
International Classes:
H03L7/06; H03L7/099; H03L7/10; (IPC1-7): H03L7/06
Attorney, Agent or Firm:
Keiichi Yamamoto