Title:
METHOD AND EQUIPMENT FOR PHASE DEVIATION CLOCK GENERATION
Document Type and Number:
Japanese Patent JPH08330948
Kind Code:
A
Abstract:
PROBLEM TO BE SOLVED: To provide a method and a device for generating plural phase shift clocks on an IC chip. SOLUTION: The device is provided with a PLL 150 provided at a first position and to generate a reference clock 170 and reference voltage 172, local clock generation circuits 152, 154 provided at a second position and a first conductor connected with the PLL 150 and the local clock generation circuits and to transmit the reference clock from the PLL 150 to the local clock generation circuit. Furthermore, the device is provided with a second conductor connected with the PLL 150 and the local clock generation circuits and to transmit the reference voltage from the PLL 150 to the local clock generation circuits. The plural phase shift clocks are generated at a second position by using the local clock generation circuits, according to the reference voltage and the reference clock.
Inventors:
SASHIYANANDAN RAJIBAN
Application Number:
JP15296996A
Publication Date:
December 13, 1996
Filing Date:
May 24, 1996
Export Citation:
Assignee:
SUN MICROSYSTEMS INC
International Classes:
H03K5/15; G06F1/06; G06F1/10; H03L7/00; H03L7/06; (IPC1-7): H03L7/00; H03K5/15
Attorney, Agent or Firm:
Takao Igarashi (1 outside)
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