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Patent Searching and Data


Title:
METHOD FOR PATTERNING ALUMINUM LAYER
Document Type and Number:
Japanese Patent JPS60249151
Kind Code:
A
Abstract:

PURPOSE: To prevent short-circuiting between an aluminum electrode and wiring by leaving no etching residue at all in patterning Al using a positive resist.

CONSTITUTION: An insulating layer 2 made of SiO2 is formed on a semiconductor substrate 1, and an Al layer 3 to be formed as the wiring layer of the first layer is formed on the layer 2. On the layer 3, a protective film 9 of a silicone resin is formed on the layer 3, and moreover on the film 9, a positive resist 4 is formed. This resist 4 is exposed and developed, and the silicone resin 9 is etched with a fluorine type gas by using the obtained positive resist 4 mask. Then, the Al layer 3 is etched by changing over said gas to a chlorine type gas, and the wiring Al layers 3, 3' separated from each other are formed.


Inventors:
TAKADA CHIYUUICHI
SUZUKI KAZUAKI
Application Number:
JP10603184A
Publication Date:
December 09, 1985
Filing Date:
May 25, 1984
Export Citation:
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Assignee:
FUJITSU LTD
International Classes:
G03C5/00; G03F7/09; (IPC1-7): G03C5/00
Domestic Patent References:
JPS5384564A1978-07-26
JPS56153736A1981-11-27
JPS476823A
Attorney, Agent or Firm:
Kugoro Tamamushi