Title:
プロセッサの効率的な制御をするための方法及び装置
Document Type and Number:
Japanese Patent JP4208149
Kind Code:
B2
Abstract:
A method is provided for the functional control of program and/or data flows in digital signal processors and processors, which have respective closed and separated modules for program and data flow control, working in parallel with computers. The method enables a power-efficient adaptation of the signal processing with the applied SIMD command-type in the individual paths and minimizes the emergence of the appearance of NOP-commands with which the VLIW-architecture of the processor must be supplied. The adaptation of the signal processing is achieved by individually controlling the parallel signal processing of the processor in the data paths (DP) which respectively belong to a first and second slice. For this purpose, a single slice halt outputted from an SSM register bank switches the register clockline according to state-dependent signal processing.
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Inventors:
Drescher Wolfram
Polst Uwe
Polst Uwe
Application Number:
JP2004504110A
Publication Date:
January 14, 2009
Filing Date:
May 13, 2003
Export Citation:
Assignee:
Philips Semiconductors Dresden Akchen Gesellshaft
International Classes:
G06F9/38; G06F9/00; G06F9/30
Domestic Patent References:
| JP2000322259A | ||||
| JP2002123331A | ||||
| JP2005525648A |
Foreign References:
| WO1999014685A1 | ||||
| US20020004916 |
Attorney, Agent or Firm:
Mitsufumi Esaki
Tsuneo Mihara
Okumura Yoshimichi
Blacksmith
Tsuneo Mihara
Okumura Yoshimichi
Blacksmith