Title:
MICROCOMPUTER
Document Type and Number:
Japanese Patent JPH11288409
Kind Code:
A
Abstract:
To attain an operation mode with low power consumption by a microcomputer.
A destination of branch address after the stop of a flash EEPROM 1 is set in a RAM destination of branch storage register 18, and a block transfer state flag 19 is set. The data of the 000H-03FFH address of the flash EEPROM 1 are block-transferred to a RAM 2. When the transfer is ended, the block transfer state flag 19 is cleared, and a clock outputted from a selector 7 is switched to a low frequency oscillator 5 side by a clock selection signal 6. The operation of the flash EEPROM 1 with large power consumption is stopped. Afterwards, a CPU 3 is operated in response to an instruction from the RAM 2.
More Like This:
| JPH0721744 | [Title of Invention] Bass Line Precharge Circuit |
| JPH0454652 | MICROCOMPUTER |
Inventors:
TOYAMA HIROSHI
Application Number:
JP9016698A
Publication Date:
October 19, 1999
Filing Date:
April 02, 1998
Export Citation:
Assignee:
NIPPON ELECTRIC IC MICROCOMPUT
International Classes:
G06F15/78; G06F1/32; G06F12/00; (IPC1-7): G06F15/78
Attorney, Agent or Firm:
Tadashi Wakabayashi (4 others)
Previous Patent: CONFIGURATION OF CLIENT SOFTWARE TO USE REMOVE NOTICE
Next Patent: HIGHLY ACCURATE ESTIMATION OF BASIC FUNCTION
Next Patent: HIGHLY ACCURATE ESTIMATION OF BASIC FUNCTION