Title:
MONOLITHIC INTEGRATED SEMICONDUCTOR CIRCUIT DISPOSITION
Document Type and Number:
Japanese Patent JPS5533098
Kind Code:
A
Abstract:
A monolithic integrated semiconductor circuit arrangement comprises at least one injection logic circuit (e.g. T11) and at least one further circuit (B). The supply currents (Iq) of the further circuits (B) are derived from the injection logic circuit, for example by providing an extra collector zone (4, in Figures 5 and 6) adjacent the injector (1, in Figures 5 and 6) of the injection circuit. In this way problems are avoided which arise when the further circuits (B) which may be interface circuits are supplied from a special peripheral power supply circuit via an intricate conductor configuration, and a fixed ratio between the injector current (Is) of the injection logic circuit (T11) and the supply currents (Iq) for the interface circuits (B) can be maintained.
Inventors:
RORUFU HOIZERU
HANSU URURITSUHI SHIYORUTSU
HANSU URURITSUHI SHIYORUTSU
Application Number:
JP10875079A
Publication Date:
March 08, 1980
Filing Date:
August 28, 1979
Export Citation:
Assignee:
PHILIPS NV
International Classes:
H01L21/8226; H01L27/02; H01L27/082; H03K19/091; (IPC1-7): H01L27/06; H03K19/08