Title:
MULTILAYERED WIRING BOARD
Document Type and Number:
Japanese Patent JP2630293
Kind Code:
B2
Abstract:
PURPOSE: To prevent the stripping off of a wiring pattern stuck to an electric insulating substrate from the substrate by press-contacting meshed thin plates of a metal having a coefficient of thermal expansion smaller than that of copper with both surfaces of a thin plate which is one of the internal layers of a multilayered wiring board.
CONSTITUTION: After conductor layers for internal wiring 20 formed by press-contacting meshed metallic plates 22 to both surfaces of a copper plate 21 are stuck to both surfaces of an electric insulating substrate 1 over the entire area of the substrate 1 and the conductor layers are patterned to the wiring 20, prepregs 4 are thermocompression-bonded to the conductor layers and external wiring 5 is formed on the prepregs 4. At the time of forming the conductor layers, the meshed thin plates of a metal having a coefficient of thermal expansion which is smaller than that of copper are press-contacted with, at least, both surfaces of the plate 21 which is one of the internal layers of a multilayered wiring board. Consequently, the substantial coefficient of thermal expansion of the wiring board can be reduced while copper foil is used from internal wiring. Therefore, the stripping off of the pattern 20 from the substrate 1 hardly occur, because the difference in coefficient of thermal expansion between the pattern 20 and substrate 1 becomes smaller.
Inventors:
Harumi Mizunashi
Application Number:
JP4017495A
Publication Date:
July 16, 1997
Filing Date:
February 28, 1995
Export Citation:
Assignee:
NEC
International Classes:
H05K1/09; H05K1/05; H05K3/46; H05K1/00; H05K1/02; (IPC1-7): H05K3/46; H05K1/09
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)
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