Title:
MULTILEVEL DYNAMIC MEMORY DEVICE HAVING OPEN BIT LINE STRUCTURE AND ITS DRIVE METHOD
Document Type and Number:
Japanese Patent JP2007164978
Kind Code:
A
Abstract:
To provide a multilevel dynamic memory device having an open bit line structure.
The multilevel dynamic memory device has a plurality of word lines, a plurality of open bit lines, and a plurality of memory cells. Each memory cell of the plurality of memory cells is connected to each word line and each bit line. The plurality of memory cells store data of at least 2 bits. Further, it has a plurality of sense amplifier sections and each sense amplifier in the plurality of sense amplifier sections amplifies the voltage difference between the plurality of bit lines at the both sides.
Inventors:
SO KIKAN
LEE YEONG-TAEK
LEE YEONG-TAEK
Application Number:
JP2006339138A
Publication Date:
June 28, 2007
Filing Date:
December 15, 2006
Export Citation:
Assignee:
SAMSUNG ELECTRONICS CO LTD
International Classes:
G11C11/56; G11C11/4091; H01L21/8242; H01L27/108
Domestic Patent References:
| JPH11163286A | 1999-06-18 | |||
| JPH09282891A | 1997-10-31 | |||
| JPH09320280A | 1997-12-12 | |||
| JPH11120759A | 1999-04-30 |
Attorney, Agent or Firm:
Yasunori Otsuka
Shiro Takayanagi
Yasuhiro Otsuka
Shuji Kimura
Shiro Takayanagi
Yasuhiro Otsuka
Shuji Kimura
Previous Patent: MULTILEVEL DYNAMIC MEMORY DEVICE
Next Patent: METHOD OF CALIBRATING DRIVER AND ODT IMPEDANCE OF SYNCHRONOUS MEMORY APPARATUS
Next Patent: METHOD OF CALIBRATING DRIVER AND ODT IMPEDANCE OF SYNCHRONOUS MEMORY APPARATUS