PURPOSE: To enable high-speed processing even when the use efficiency of a computing element is high and the plural kinds of different processing are performed.

CONSTITUTION: This device is provided with selectors 51-54 for selecting data to be supplied to the respective input terminals of a full adder 57 and a multiplier 58, filter and reverberate registers 55 and 56 to write/read the added result of the full adder 57, and delay elements D1-D9 and 3D to delay data interposed suitably between these filters just for prescribed time. The selection of the selectors 51-54 and the write/read of the filter register 55 and reverberate register 56 are controlled by control programs corresponding to arithmetic. The plural control programs are provided corresponding to arithmetic and perform control so as not to execute the different kinds of arithmetic at the same timing in the full adder 57 and the multiplier 58.