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Patent Searching and Data


Title:
MOUNTING METHOD OF SEMICONDUCTOR COMPONENT
Document Type and Number:
Japanese Patent JPH0582951
Kind Code:
A
Abstract:

PURPOSE: To mount a semiconductor component accurately to a printed circuit board, in which a wide wiring pattern such as a power line and a narrow wiring pattern such as a signal line are mixed.

CONSTITUTION: When bumps 2a, 2b formed to the electrodes of a semiconductor chip 1 are abutted against corresponding wiring patterns 3a, 3b composed of conductive ink printed on a printed circuit board 4 and the semiconductor chip 1 is connected electrically to the printed circuit board 4, the wiring pattern 3a having board line width in the wiring patterns 3a, 3b on the printed circuit board 4 side is formed by printing narrow wiring patterns 3a1, 3a2 consisting of conductive ink in parallel at an interval A2 of a limiting minimum interval or less capable of separating lines by printing.


Inventors:
TAKAISHI MASAKATSU
Application Number:
JP24186991A
Publication Date:
April 02, 1993
Filing Date:
September 20, 1991
Export Citation:
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Assignee:
SHARP KK
International Classes:
H01L21/60; H05K3/34; H05K1/11; H05K3/12; (IPC1-7): H01L21/60; H05K3/34
Attorney, Agent or Firm:
Nishikyo Keiichiro (1 outside)