Title:
【発明の名称】復調システム
Document Type and Number:
Japanese Patent JP2586169
Kind Code:
B2
Abstract:
In a demodulating system for demodulating a modulated signal into decoded signals (S11 min -12 min , S21 min -22 min ), an error signal correcting circuit (55) is used in correcting discrimination error signals (Ep, Eq) supplied from a demodulator (52) in compliance with error location signals (Sp1-2, Sq1-2) supplied from an error-correcting decoder (54) and in producing corrected discrimination error signals (Ep min , Eq min ) for supply to an adaptive equalizer (51) which is additionally supplied with polarity signals (Dp, Dq) from a delay circuit (53). The modulated signal is equalized in accordance with the corrected discrimination error signals and the polarity signals, demodulated into demodulated signals and the discrimination error signals, and error corrected and decoded into the decoded signals. The delay circuit delays P-channel and Q-channel polarity bits of the demodulated signal into the polarity signals. The error-correcting decoder produces the error location signals by using P-channel and Q-channel error correcting code bits of the demodulated signals. The modulated signal may be supplied first to the demodulator and then to the equalizer.
More Like This:
| JPH04352523 | DATA TRANSMISSION DEMODULATOR |
| JPS60137116 | WAVEFORM EQUALIZER |
Inventors:
MIZOGUCHI SHOICHI
Application Number:
JP5282090A
Publication Date:
February 26, 1997
Filing Date:
March 06, 1990
Export Citation:
Assignee:
NIPPON ELECTRIC CO
International Classes:
H03H15/00; H04B3/04; H04B3/06; H04L1/00; H04L1/20; H04L25/03; H04L27/00; H04L27/01; H04L27/38; (IPC1-7): H04B3/06; H04L27/01; H04L27/38
Domestic Patent References:
| JP57159136A | ||||
| JP1196924A | ||||
| JP63204947A | ||||
| JP63119331A | ||||
| JP643406B2 |
Attorney, Agent or Firm:
Yosuke Goto (2 outside)