PURPOSE: To obtain a sampling clock always proportional to (n) times the frequency of an input signal by connecting a high pass filter(HPF) for removing a DC component to a signal input part in a sampling clock generating circuit.
CONSTITUTION: When an input signal to which positive DC voltage e.g. is superposed is applied to the HPF 2a and a waveform obtained by removing a DC voltage component is outputted. The output of the HPF 2a is applied to a succeeding low pass filter(LPF) 2 to remove a noise component and the original waveform of the input signal is restored and applied to a waveform shaping circuit 3. The circuit shapes the waveform of the signal applied from the LPF 2 to a square wave with 50% duty ratio by a zero-crossing comparator and outputs the shaped signal to a PLL circuit 4. The PLL circuit 4 compares the phase of the square wave signal applied from the shaping circuit 3 with that of a signal obtained by dividing oscillation frequency from an internal oscillator into 1/n frequency and controls oscillation frequency so that the phase of the 1/n frequency demultiplied signal is synchronized with that of the square wave signal.
YODA HIDEAKI
YODA SHOZO
