Title:
NITRIDE SEMICONDUCTOR LAMINATE AND NITRIDE SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JP2016096298
Kind Code:
A
Abstract:
PROBLEM TO BE SOLVED: To provide a technology for suppressing generation of warpage at a nitride semiconductor laminate.SOLUTION: A nitride semiconductor laminate comprises a nitride semiconductor layer provided on any one principal surface of a substrate. The nitride semiconductor layer is configured by alternately laminating a first nitride semiconductor layer and a second nitride semiconductor layer a predetermined number of times. The first nitride semiconductor layer further contains an impurity element that reduces warpage generated at the nitride semiconductor laminate, and is formed so that a concentration of the impurity element in the first nitride semiconductor layer becomes higher than that of in the second nitride semiconductor layer.SELECTED DRAWING: Figure 1
Inventors:
TAKEUCHI TAKASHI
KONNO TAICHIRO
KONNO TAICHIRO
Application Number:
JP2014232632A
Publication Date:
May 26, 2016
Filing Date:
November 17, 2014
Export Citation:
Assignee:
SUMITOMO CHEMICAL CO
International Classes:
H01L21/205; H01L33/32
Attorney, Agent or Firm:
Fukuoka Masahiro
Hiromi Abe
Hideo Tachibana
Masahiro Shiratori
Hiromi Abe
Hideo Tachibana
Masahiro Shiratori