Title:
NON-VOLATILE SEMICONDUCTOR MEMORY
Document Type and Number:
Japanese Patent JP2004103211
Kind Code:
A
Abstract:
To provide a four-level flash memory in which a verification margin can be stably insured as the most important characteristic .
For example, a reference current generation circuit 41 for generating reference currents IrefO, Iref1, and Iref3 for the purpose of comparison of the currents Icell flowing from respective memory cells MC of a memory cell array 32 to bit lines BL0 to BLk is provided with amplifier circuits 41a-3, 41b-3 and 4c-3 for amplifying the currents flowing in reference cells in such a manner that the ratio of the amplification rates of the currents during verification of writing to the amplification rates of the current during reading out of data is made greater than 1.
Inventors:
TANZAWA TORU
Application Number:
JP2003193728A
Publication Date:
April 02, 2004
Filing Date:
July 08, 2003
Export Citation:
Assignee:
TOSHIBA CORP
International Classes:
G11C16/06; G11C11/56; G11C16/02; G11C16/28; H01L21/822; H01L21/8247; H01L27/04; H01L27/10; H01L27/115; H01L29/788; H01L29/792; (IPC1-7): G11C16/06; G11C16/02; H01L21/822; H01L21/8247; H01L27/04; H01L27/10; H01L27/115; H01L29/788; H01L29/792
Attorney, Agent or Firm:
Takehiko Suzue
Satoshi Kono
Makoto Nakamura
Kurata Masatoshi
Sadao Muramatsu
Ryo Hashimoto
Satoshi Kono
Makoto Nakamura
Kurata Masatoshi
Sadao Muramatsu
Ryo Hashimoto