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Title:
OFFSET VOLTAGE CORRECTION CIRCUIT AND FM RECEIVER
Document Type and Number:
Japanese Patent JPH0936770
Kind Code:
A
Abstract:

To realize the offset voltage correction circuit eliminating a DC offset voltage from a detection signal without arranging a detection circuit and a 2nd local oscillation circuit in the same IC.

When a 2nd intermediate frequency signal having the same carrier frequency as an oscillating frequency of a 2nd local oscillation circuit outputted from a 2nd mixer 7 is detected by an FM detection circuit 10 and when a DC offset voltage is generated in a detection signal outputted from the FM detection circuit 10 resulting from deviation in the oscillating frequency of the 2nd local oscillation circuit 8 or a deviation in the center frequency of an S curve characteristic of the FM detection circuit 10, an oscillation signal of the 2nd local oscillation circuit 8 is detected by an FM detection circuit 12 with the same characteristic as that of the FM detection circuit 10. Since the same offset voltage as the offset voltage is obtained, the DC offset voltage is eliminated by subtracting the DC offset voltage from the DC offset voltage included in the detection signal by a subtractor circuit 13.


Inventors:
SAEKI GENICHI
KUROKI KATSUICHI
SHONO HIROSHI
Application Number:
JP18034295A
Publication Date:
February 07, 1997
Filing Date:
July 17, 1995
Export Citation:
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Assignee:
SONY CORP
International Classes:
H03D3/00; H03F3/34; H04B1/26; (IPC1-7): H04B1/26; H03D3/00; H03F3/34
Attorney, Agent or Firm:
Takahisa Sato



 
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