Login| Sign Up| Help| Contact|

Patent Searching and Data


Title:
OPERATION PROCESSOR
Document Type and Number:
Japanese Patent JPS6072025
Kind Code:
A
Abstract:

PURPOSE: To shorten an instruction executing time by providing two circuits for both addition and subtraction use, on a circuit connected to a carry-in input, a carry-out output and a data output of a decimal adder.

CONSTITUTION: A decimal adding part 1 is constituted of a decimal adder 3, a data holding means 6, a data selecting means 7, etc. Codes of the first and the second operands which are inputted are held by a holding means 2, and sent to the selecting means 7. The adder 3 has two data inputs, has a function for adding and subtracting both of them, and also has a carry-in input and a carry- out output for processing an operand being larger than the number of characters which can be processed at the same time by dividing it into several times. A carry-out holding means 5 adds and subtracts an output of the adder 3 and holds it separately, sends it to a carry-in data selecting circuit 4, and selects it to match an operating mode. Each data output which has been held is selected and outputted by a code of said operand, etc. by the data selecting means 7.


Inventors:
SHIMODA WATARU
Application Number:
JP18154383A
Publication Date:
April 24, 1985
Filing Date:
September 28, 1983
Export Citation:
Click for automatic bibliography generation   Help
Assignee:
NIPPON ELECTRIC CO
International Classes:
G06F7/494; G06F7/495; G06F7/50; G06F7/507; (IPC1-7): G06F7/50
Attorney, Agent or Firm:
Yutaro Kumagai