Title:
PAINT-OUT CONTROL CIRCUIT
Document Type and Number:
Japanese Patent JPS6075966
Kind Code:
A
Abstract:
PURPOSE:To detect at a high speed a paint-out boundary with simple hardware by setting the boundary information for each plain memory and leading each boundary coincidence/dissidence signal of each plain memory to a logical circuit to detect the paint-out boundary. CONSTITUTION:The boundary information is set every plain memory to a comparison value register 31 to designate an ON or OFF bit of the graphic pattern information as the paint-out boundary. A comparator 32 compares the contents of the register 31 with the output contents of a plain memory 14. The mask information is set to a mask register 33 to designate a plain excluded from the subject of detection for the paint-out boundary. Then the mask information is supplied to a mask circuit 34 to mask the output of the comparator 32. An AND gate 35 produces a logical signal to show whether or not the paint- out boundary is obtained according to each boundary coincidence/dissidence signal for each plain memory which is delivered from the circuit 34.
Inventors:
HASEBE TSUNENORI
Application Number:
JP18272783A
Publication Date:
April 30, 1985
Filing Date:
September 30, 1983
Export Citation:
Assignee:
TOSHIBA KK
International Classes:
G06T11/40; G06T5/00; (IPC1-7): G06F15/62
Attorney, Agent or Firm:
Takehiko Suzue