Title:
PHASE SYNCHRONIZATION LOOP CIRCUIT, SEMICONDUCTOR INTEGRATED CIRCUIT, AND RECEIVER
Document Type and Number:
Japanese Patent JP2007312334
Kind Code:
A
Abstract:
To obtain a phase synchronization loop circuit which can efficiently select a voltage controlled oscillator to be used, and set its oscillation frequency range.
A controller 103 of a phase synchronization loop circuit 100 selects a voltage control oscillator with a main oscillation frequency range including a channel selection frequency from among a plurality of voltage controlled oscillators VCO1-VCOn as a voltage control oscillator connected to the phase synchronization loop circuit 100, and then sets the oscillation frequency range of the selected voltage controlled oscillator in a sub-oscillation frequency range including the channel selection frequency.
COPYRIGHT: (C)2008,JPO&INPIT
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Inventors:
AMANO SHINJI
Application Number:
JP2006142130A
Publication Date:
November 29, 2007
Filing Date:
May 22, 2006
Export Citation:
Assignee:
SHARP KK
International Classes:
H03L7/18; H03L7/099; H04B1/26
Attorney, Agent or Firm:
Kenzo Hara International Patent Office