Title:
PICTURE DATA PROCESSOR
Document Type and Number:
Japanese Patent JP3948645
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To prevent the generation of excess or shortage in the extraction of picture data on a downstream due to a delay generated in picture data processing executed in a DSP and to thin out picture data in a subscanning direction.
SOLUTION: The picture data processor 400 is provided with plural arithmetic units 401, 402, 407 for processing picture data included in a signal based on main scanning and subscanning gate signals, a DSP 403 arranged between both the arithmetic units, a 1st delay 408 for delaying a main scanning gate 'lgate' annexed to the picture data supplied to the DSP 403 by the number A of pixels, a 2nd delay 411 for delaying a subscanning gate 'fgate' by the number B of lines, and a thinning device 414 for thinning out the gate 'lgate' by regular C/D. The 2nd delay 411 counts up main scanning gates lgate' delayed by the 1st delay 408 or subscanning synchronization lsync' by the number B and delaying the gate 'fgate' as fgate' and the thinning device 414 thins out the gate lgate' delayed by the 1st delay 408 by C/D and outputs the thinned gate.
Inventors:
Hiroyuki Kawamoto
Application Number:
JP21851599A
Publication Date:
July 25, 2007
Filing Date:
August 02, 1999
Export Citation:
Assignee:
株式会社リコー
International Classes:
H04N1/40; G06T1/00; (IPC1-7): H04N1/40; G06T1/00
Domestic Patent References:
| JP9305755A | ||||
| JP9116737A | ||||
| JP11205537A | ||||
| JP10262221A |
Attorney, Agent or Firm:
Nobuoki Sugi