To provide a PLL circuit and the semiconductor integrated circuit using it where high speed lockup of PLL is realized and a PLL operation is made stable.

This PLL circuit, that is built in the semiconductor integrated circuit such as a single chip microcomputer, is provided with a phase compactor 1 that compares a phase of a reference clock with that of a feedback clock, a charge pump 2 that charges/discharges a capacitor, a voltage controlled oscillator 3 the oscillating frequency is controlled, a frequency divider circuit 4 that frequency-divides the feedback clock, and a feedback path interrupt means 5 that interrupts a feedback path around an objective oscillating frequency. The feedback path interrupt means 5 is made up of a control signal generating circuit 7 that detects an oscillator control voltage of the capacitor 6 and a feedback control circuit 8 that activates/inactivates the clock operation of the feedback path by its output signal. When the oscillator control voltage is lower than a reference voltage, the clock operation of the feedback path is stopped to charge the capacitor 6 from a GND level up to a reference voltage level at a high speed.