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Patent Searching and Data


Title:
PLL CIRCUIT
Document Type and Number:
Japanese Patent JP2000332602
Kind Code:
A
Abstract:

To cancel fluctuation to ground or a power source and influences of noise from electromagnetic field interference from an antenna by equipping a voltage control oscillator for oscillation outputting a differential voltage signal and a frequency divider for frequency dividing the differential output signal of the voltage control oscillator and outputting it as another signal of a phase comparator.

In a voltage control oscillator 5, an oscillation frequency is controlled by a potential difference between an SLPF1 and an SLPF2 of output signals of a loop filter 4, output signals fvco1 and fvco2 are differentially outputted and its output differential voltage signal is inputted to a frequency divider 6. The frequency divider 6 inputs the differential voltage signals thus inputted to a phase comparator 2 as output signals by frequency dividing them into voltage signals fc. In this way, since all the voltage signal paths are received and delivered with the differential voltage signals, it is possible to cancel influences of noise accompanying potential change of a ground or a power source and noise of the same phase to electromagnetic field interference by a radiation electromagnetic wave of an antenna.


Inventors:
YOKONAGA HIROYUKI
SAKAKURA MAKOTO
ANDO TOSHIAKI
ISHIDA KAORU
Application Number:
JP14058599A
Publication Date:
November 30, 2000
Filing Date:
May 20, 1999
Export Citation:
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Assignee:
MATSUSHITA ELECTRIC IND CO LTD
International Classes:
H03L7/08; H03B5/12; H03L7/093; H03L7/099; (IPC1-7): H03L7/08; H03L7/093; H03L7/099
Attorney, Agent or Firm:
Masamichi Matsuda