PLL CIRCUIT - 富士通株式会社

Title:

PLL CIRCUIT

Document Type and Number:

Japanese Patent JP3560696

Kind Code:

B2

Abstract:

PROBLEM TO BE SOLVED: To automate matching with locked frequency by providing this phase locked loop(PLL) circuit with a PLL including a voltage controlled oscillator(VCO), a counting means, a counting period setting means, a comparing/judging means, and a physical quantity generating means for generating physical quantity related to a change in the oscillation frequency of the VCO.
SOLUTION: The comparing/judging means 24 compares the count value A of the counting means 22 with a prescribed reference value B, and a state A<B (the count value A is smaller than the reference value B, a state A=B (both the values are equal) or a state A>B (the count value A is larger than the reference value B) is discriminated. The physical quantity generating means 25 generates physical quantity related to a change in the oscillation frequency of the VCO 21 in accordance with the judged result of the means 24. The means 25 generates physical quantity for increasing the oscillation frequency of the VCO 21 when A<B, and when A=B, outputs the oscillation frequency of the VCO 21 as it is. When A>B, the means 25 outputs physical quantity for reducing the oscillation frequency of the VCO 21. Consequently the matching of free-running frequency with locked frequency can be automated only by one VCO.

Inventors:

Shinichi Shiozu
Masaya Tamamura
Noboru Oishi

Application Number:

JP17310995A

Publication Date:

September 02, 2004

Filing Date:

July 10, 1995

Export Citation:

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Assignee:

富士通株式会社

International Classes:

H03L7/099; H03B5/08; H03B5/20; (IPC1-7): H03L7/099; H03B5/08; H03B5/20

Domestic Patent References:

JP7095109A
JP6291650A

Foreign References:

US4590440
US4580107

Attorney, Agent or Firm:

Gunichiro Ariga

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