To shorten a lock-up time while maintaining frequency stability during PLL lock.

This PLL circuit is provided with a phase comparator 1 for comparing a reference signal S0 with a PLL feedbacked comparison signal S2, and for outputting a phase delay (advance) signal 11(12) for turning the phase difference period of the delay (advance) of the comparison signal against the reference signal into an L(H) active level, and a charge pump circuit 21 for inputting the signals 11 and 12, and for charging and discharging a capacitor CO of an LPF, and a VCO 4 for oscillation outputting a PLL circuit output signal S1 with frequencies corresponding to the smoothing voltage of the C0, and a frequency-dividing circuit 5 for frequency-dividing the signal S1 at a prescribed rate, and for outputting the comparison signal S2. This PLL circuit is also provided with a phase delay (advance) signal delaying circuit 81(82) for preparing a signal for delaying only the start point of the active period of the phase delay (advance) signal 11(12), and for operating a charge pump circuit 22. Only when a phase difference between the signals S0 and S2 is larger than the delay time, the charging and discharging currents of the capacitor C0 are made large according to the operation of the circuit 22 so that a lock-up time can be shortened.