PROGRAMMABLE LOGIC DEVICE STRUCTURE

Title:

PROGRAMMABLE LOGIC DEVICE STRUCTURE

Document Type and Number:

Japanese Patent JP2000201066

Kind Code:

A

Abstract:

To provide a large capacity programmable logic device structure capable of eliminating the need for any excessive amount of interconnection conductor resources on a device.

In a programmable logic device 10, plural large areas 20 arranged in a second-dimensional array constituted of crossing lines and columns are provided on this device. Each large area 20 is provided with plural programmable logic areas 30 and a programmable memory area 40. Each logic area 30 is provided with plural small areas 50 constituted of programmable logics. Each large area 20 is provided with connected interconnection resources so that communication between the logics in the large area and the memory area 40 can be attained without using any huge inter-large area interconnection resources arranged on this device in the same way for relative local interconnection.

Inventors:

JEFFERSON DAVID E
CAMERON MCCLINTOCK
SCHLEICHER JAMES
ANDY L LEE
MEJIA MANUEL
PEDERSEN BRUCE B
LANE CHRISTOPHER F
CLIFF RICHARD G
SURINIBASU T REDI

Application Number:

JP32754999A

Publication Date:

July 18, 2000

Filing Date:

November 17, 1999

Export Citation:

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Assignee:

ALTERA CORP

International Classes:

H03K19/173; H03K19/177; H01L21/82; (IPC1-7): H03K19/173; H01L21/82

Attorney, Agent or Firm:

Haruo Hamada

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