To provide a polyphase clock generating circuit which can form a polyphase clock having a narrow phase difference without necessity of either the rapidity of a reference clock or the high speed operation of a flip-flop.

In the polyphse clock generating circuit for forming a plurality of output clocks having different phases based on the reference clock, first and second reference clocks (clka, clkb) having different phases are frequency divided to form the output clock. The polyphase clock generating circuit includes first and second frequency dividing circuits (diva, divb), and a switch for intermittently short circuiting between predetermined nodes (divbx-qx, divax-qx) of the first and second frequency dividing circuits. The switch short-circuits between the predetermined nodes at the timing controlled by the same level as the predetermined node in a stationary operation state. More particularly, the switch is controlled to be short-circuited by either or both of the first and second reference clocks. The independently operating frequency dividing circuit frequency-divides the reference clocks having different phases, generates the output clocks with different phases, adjusts the operations of both the frequency dividing circuits by a short circuiting switch, and adjusts the phase deviation of the frequency dividing clocks generated from the frequency dividers.