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Title:
POWER SOURCE FEED CIRCUIT SUBSTRATE
Document Type and Number:
Japanese Patent JPS60178648
Kind Code:
A
Abstract:

PURPOSE: To enable the flattening of the gain characteristic, enlargement of band, and improvement in isolation characteristic by a method wherein a line is reduced in characteristic impedance and terminated at the characteristic impedance in an AC manner.

CONSTITUTION: Alumina of γ10 or the like is used for a dielectric substrate 1 to realize the characteristic impedance of a signal line 3 at 50Ω or 75Ω; whereas, a substrate 9 of high dielectric constant is used for a power source feed substrate to reduce the characteristic impedance of a power source feed line pattern 4. Actually, γ3,000 is being realized, and the characteristic impedance can be reduced to approx. 1Ω if the line width is 1mm and the substrate thickness is 0.2mm. Besides, adhesion of respective substrates can be realized satisfactorily with no problem even through the thermal process during chip assembly by the use of Ag paste of polyimide series or the like. Resistors 10 terminate the feed line pattern 4 at its characteristic impedance in an AC manner, and are formed by a thin film or thick film technique.


Inventors:
AKAZAWA YUKIO
ISHIHARA NOBORU
OBARA MAMORU
Application Number:
JP3426484A
Publication Date:
September 12, 1985
Filing Date:
February 27, 1984
Export Citation:
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Assignee:
NIPPON TELEGRAPH & TELEPHONE
International Classes:
H01L23/12; H01L23/15; H01L23/64; (IPC1-7): H01L23/12
Attorney, Agent or Firm:
Tsuneo Shiramizu



 
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