To attain a high print speed furthermore.

Plural (e.g. four) sets of video data generating circuits 40 and page memories 27 are provided and division read input means 23, 24 and a synthesis output circuit 50 are provided and image data stored in an image data memory 60 are distributed to page video data generating circuits 40A, 40B, 40C, 40D which generate division page video data PVDA, PVDB, PVDC, PVDD in parallel. Then the division video data PVDA, PVDB, PVDC, PVDD generated in parallel are synthesized and the generating speed by the video data generating circuits 40A, 40B, 40C, 40D is selected to be the same as a generating speed by a conventional video data generating circuit 40 to increase the transfer output speed of the video data PVD to an engine 31.