To enhance reliability of wiring by enhancing deposition selectivity of a catalytic metal layer being formed when a cap barrier layer is formed on the surface of a metallization and reducing damage on the metallization when the catalytic metal layer is deposited.
In the process for fabricating a semiconductor device comprising steps for forming a catalytic metal layer 17 by immersion plating only on a metallization 16 formed on an insulating film 12 on a substrate 11 and for forming a cap barrier layer 18 selectively on the metallization 16 by electroless plating utilizing the catalytic metal layer 17, the step for forming the catalytic metal layer 17 by immersion plating employs such a catalytic plating liquid as the ζ-potential on the insulating film 12 and the ζ-potential on the metallization 16 have different polarities. In order to reduce damage on the metallization, concentration of palladium in a palladium immersion plating liquid being used in immersion plating for forming the catalytic metal layer and the etching amount of metal are optimized.
SEGAWA YUJI
NOGAMI TAKESHI
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