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Title:
SOLID STATE IMAGING DEVICE AND ITS MANUFACTURING METHOD
Document Type and Number:
Japanese Patent JP2004273792
Kind Code:
A
Abstract:

To solve a problem that, when a high voltage is used at a charge detecting section, since an MOS (metal oxide semiconductor) transistor having a high breakdown voltage must be used in the post-stage, it is disadvantageous for making a peripheral circuit fine in structure, high in operation speed and low in power consumption.

When a horizontal CCD (charge-coupled device) 14 is manufactured in a CCD imaging device of a horizontal CCD structure, a transfer channel is formed such that the potential becomes shallower gradually toward the output side at least at the output part, preferably a transfer part on the outside of the region of a pixel part 11, thus setting a shallow potential at the FD (floating diffusion) part of a charge detecting section 15. Consequently, voltage reduction can be realized at the charge detecting section 15 while ensuring sufficient characteristics at the FD part.


Inventors:
YASUDA MINORU
HIROTA ISAO
NOGUCHI KATSUNORI
TOYAMA TAKAYUKI
YAMAGISHI KATSUMI
Application Number:
JP2003062917A
Publication Date:
September 30, 2004
Filing Date:
March 10, 2003
Export Citation:
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Assignee:
SONY CORP
International Classes:
H01L27/148; H01L21/339; H01L29/762; H04N5/335; H04N5/369; H04N5/372; (IPC1-7): H01L27/148; H01L21/339; H01L29/762; H04N5/335
Attorney, Agent or Firm:
Funabashi Kuninori