To achieve high-speed address conversion from a logical address into a physical address, and to improve performance of a processor by preventing TLB thrashing.

When a TLB comparison part 20 determines a TLB error in a logical address of a page to be accessed by a program, and an EAB comparison part 21 determines that the logical address does not exist in an EAB 17 in which already accessed logical addresses are included, a delay control part 22 delays timing of reading a correspondence entry from a page table 25 by predetermined time. Then, a page table reading part 23 reads the correspondence entry from the page table 25. Then, a registration part 24 registers a new entry for relating the physical address indicated by the read entry in the TLB 16, and an address conversion part 19 converts the logical address into a physical address on the basis of the entry of the TLB 16.