Title:
PROGRAMMABLE CONTROLLER
Document Type and Number:
Japanese Patent JPS6441005
Kind Code:
A
Abstract:
PURPOSE:To check the items related to an input instruction in a short time by storing both the information on the double application of the output instruction and the information on the inhibition of output into the same address of a memory means with correlation secured between both information. CONSTITUTION:A 2nd memory means 300 stores the 1st information showing the application state of an output instruction included in a program and the 2nd information showing whether the instruction address of the output instruction belongs to an output inhibiting area or not with correlation secured between both information. Then the output instruction extracted out of the program stored in a 1st memory means 100 via a 2nd extracting means 200 undergoes simultaneously its outputs to the output inhibiting area as well as its double application via the deciding means 500 and 600 based on the 1st and 2nd information stored in the memory 300. In such a way, just a single setting action suffices for a read address in case both the 1st and 2nd information are read by a reading means 400. Thus the checking time is shortened for the output instruction.
Inventors:
SAITO SUSUMU
TSUNODA TETSUO
TSUNODA TETSUO
Application Number:
JP19641687A
Publication Date:
February 13, 1989
Filing Date:
August 07, 1987
Export Citation:
Assignee:
FUJI ELECTRIC CO LTD
International Classes:
G06F11/28; G05B19/04; G05B19/048; G05B19/05; (IPC1-7): G05B19/04; G06F11/28
Domestic Patent References:
| JPS55166757A | 1980-12-26 | |||
| JPS55146533A | 1980-11-14 | |||
| JPS6065332A | 1985-04-15 | |||
| JPS5328346A | 1978-03-16 |
Attorney, Agent or Firm:
Yoshikazu Tani