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Patent Searching and Data


Title:
PROTECTING SYSTEM FOR MULTI-BYTE DATA IN STAND-BY RAM
Document Type and Number:
Japanese Patent JPS6346558
Kind Code:
A
Abstract:

PURPOSE: To restore the multi-byte data stored in a stand-by RAM to the normal data even through the multi-byte data is destructed by the OFF of a main power supply, by using an address holding means, a read/write signal holding means and a data holding means.

CONSTITUTION: A 1st and 2nd data registers 16 and 17 in a microcomputer 1 store the higher and lower bytes of the 2-byte data to be rewritten previously when an arithmetic processor MPU 10 rewrites data into the 2-byte data stored in a stand-by RAM 13. An address latch circuit 18 latches the contents of an address bus AB by the timing of a latch signal L. While a read/write signal latch circuit 19 latches the state of the read/write signal line of a control bus CB by the timing of the signal L. Then registers 16 and 17 and circuits 18 and 19 are actuated by the stand-by voltage Vs and the contents of these registers and circuits are held even in an OFF mode of an ignition switch 3. Thus the multi-byte data stored in the RAM 13 if destructed by the OFF of a main power supply can be restored to the normal data.


Inventors:
OGAWA HIROSHI
Application Number:
JP19020286A
Publication Date:
February 27, 1988
Filing Date:
August 13, 1986
Export Citation:
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Assignee:
FUJITSU TEN LTD
International Classes:
G06F12/16; G06F1/30; (IPC1-7): G06F12/16
Attorney, Agent or Firm:
Nishikyo Keiichiro