PURPOSE: To perform the DMA transfer between buses with the highest performance and the maximum efficiency of each bus and regardless of the performance of each bus, by dividing the transfer of data between two buses into the bus/data transfer and the data memory/bus transfer respectively.

CONSTITUTION: The bus connection control parts 1 and 3 and the driver receivers 4 and 6 are connected to buses A and B respectively. Then a data transfer control part 2 is added together with a data buffer memory 5. Both parts 1 and 3 perform the interface control between both buses A and B and produce various bus control signals for bus arbitration, addresses, etc. Then the transfer of data between both buses is divided into the transfer between the bus A and the memory 5 and transfer between the bus B and the memory 5. Therefore the arbitration jobs are possible independently of each other between buses A and B. In addition, the DMA transfer is attained between both buses with the highest performance and the maximum efficiency of each bus and regardless of the performance of each bus by increasing the data transfer timing speed up to a level at which the speed of the memory 5 can follow the bus of a higher bus.