PURPOSE: To obtain a pulse density modulator whose circuit design is easy by connecting plural stages of means converting a signal into a PCM signal having a few bit length and a high clock frequency in cascade.

CONSTITUTION: Data bit length reduction circuits 1∼4 are connected in cascade over plural stages and a quantized PCM signal X is inputted to an adder 11 of the data bit length decrease circuit 1 of the 1st stage. Then a pulse density modulation signal Yn of the PCM signal X is obtained at a number of bits limiting circuit 45 of the data bit length decrease circuit 4 of the n-th stage the same as the principle of a conventional puse density modulator. The data with a long bit length is processed comparatively at a low speed in the initial stage of the plural stages, while the final stage of the plural stages applies the processing of the data having a short bit length at a comparatively high speed and the circuit constitution of an adder and a memory or the like is simplified. Thus, the circuit design of the pulse density modulator is facilitated.