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Title:
PULSE GENERATING CIRCUIT
Document Type and Number:
Japanese Patent JPS62125599
Kind Code:
A
Abstract:

PURPOSE: To obtain a circuit of a high degree of integration that is suited to a defect relieving circuit which receives a specific address signal and produces a negative or positive pulse, by incorporating a programmable element to an address comparator.

CONSTITUTION: The reference voltage of a current switching type logic circuit is applied to a terminal N1 and the voltage of a constant level is applied to a terminal N2 respectively. When a fuse F21 is cut, the current of a current source I11 flows to a resistance R11 via a transistor Q11 as long as the address signal has a high level of voltage at a node A1. Thus an emitter CO11 of an emitter follower Q31 has a low potential and the output PO is set at a low potential through a fuse F11. When the node A1 is set at a low level of voltage, the collector, the CO11 and the PO are set at low potentials. In the same way, the PO has a low potential when the node A1 is kept at a low level of voltage if the fuse F11 is cut. Therefore all outputs are negative when a specific address is supplied by cutting the fuses F11WF2m are cut in response to said specific address. Then the negative pulses are produced.


Inventors:
MATSUMOTO MASAAKI
HONMA NORIYUKI
YAMAGUCHI KUNIHIKO
KANETANI KAZUO
NANBU HIROAKI
KAWAJIRI YOSHIKI
TANI KAZUHIKO
OHATA KENICHI
Application Number:
JP26489885A
Publication Date:
June 06, 1987
Filing Date:
November 27, 1985
Export Citation:
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Assignee:
HITACHI LTD
HITACHI DEVICE ENG
International Classes:
G11C29/00; G11C17/00; G11C17/06; G11C29/04; (IPC1-7): G11C17/06; G11C29/00
Attorney, Agent or Firm:
Katsuo Ogawa



 
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