QUANTIZER FOR DIGITAL SIGNAL

Japanese Patent JP3170929

B2

PURPOSE: To reduce the required amount of transmission data of quantization bits generated at every block.
CONSTITUTION: The dynamic range DR of the block that is the difference of the maximum value MAX and the minimum value MIN is found at a subtraction circuit 7. A quantization step width generation circuit 9 generates quantization step width suitable for the dynamic range. Each image data from which the minimum value MIN is eliminated is quantized at a quantization circuit 11 with the quantization step width Δ, and for example, a code signal DT of constant four bits is generated. Four sub blocks are formed by dividing one block. A comparator 13 compares the dynamic range DR' of the sub block with a threshold value TH-P, and generates an ID flag. The ID flag is supplied to a data conversion circuit 12, and in the sub block whose DR' is smaller than the threshold value TH-P, one representative code is generated from the data conversion circuit 12.

JPH08504046	INDUSTRIAL APPLICABILITY A device for converting a floating-point binary number into a logarithm in a binary format or vice versa.
JPH02501024	[Title of the Invention] PCM signal coding
JP3318823	DIGITAL SIGNAL PROCESSING DEVICE AND METHOD

Tetsujiro Kondo
Yasuhiro Fujimori

JP2198193A

May 28, 2001

January 14, 1993

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ソニー株式会社

H03M7/50; G06T9/00; H04N1/41; H04N1/415; H04N7/24; H04N19/00; H04N19/115; H04N19/126; H04N19/13; H04N19/136; H04N19/14; H04N19/176; H04N19/196; H04N19/423; H04N19/46; H04N19/65; H04N19/70; H04N19/85; H04N19/91; H04N19/98; (IPC1-7): H03M7/50; G06T9/00; H04N1/41; H04N7/24

JP61144989A
JP6292620A
JP62128621A
JP1114177A
JP63158989A
JP3214987A
JP4189089A
JP4302534A

Masatomo Sugiura

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