Title:
受信回路及び半導体集積回路
Document Type and Number:
Japanese Patent JP6849903
Kind Code:
B2
Abstract:
A reception circuit includes a determination circuit including comparator circuits configured to determinate a level of a received signal and a logic circuit configured to generate a digital signal based on outputs of the comparator circuits. The determination circuit is configured to determinate by a first number of the comparator circuits when the received signal is a first signal which is a multivalued signal and determinate by a second number of the comparator circuits, the second number being smaller than the first number, when the received signal is a second signal. The logic circuit is configured to operate as a decoder which decodes outputs of the comparator circuits and generates the digital signal when the received signal is the first signal, and operates as a selector which selects an output of the comparator circuit for generating the digital signal when the received signal is the second signal.
Inventors:
Shindai Kudo
Application Number:
JP2016198308A
Publication Date:
March 31, 2021
Filing Date:
October 06, 2016
Export Citation:
Assignee:
Socionext Inc.
International Classes:
H03K9/02
Domestic Patent References:
| JP2010288237A | ||||
| JP2011511564A | ||||
| JP2012253661A | ||||
| JP2013229776A |
Foreign References:
| US20050201491 | ||||
| US20110311008 | ||||
| US9699009 | ||||
| US20040141567 |
Attorney, Agent or Firm:
Takayoshi Kokubun