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Patent Searching and Data


Title:
RECORDING CONTROL CIRCUIT
Document Type and Number:
Japanese Patent JPS5841453
Kind Code:
A
Abstract:

PURPOSE: To freely stop a recorder accurately while no recording is required, by delaying an audio signal in matching with a mechanical delay of the recorder, and recording the audio signal to be recorded entirely.

CONSTITUTION: Left and right outputs of an FM receiver 1 are A/D-converted with ADPCM at audio analyzers 2a and 2b and stored in storage devices 3a and 3b. Audio synthesizers 4a and 4b perform D/A conversion. On the other hand, a comparison circuit 5 compares the output of the analyzers 2a and 2b and a counter 6 is incremented or decremented depending on coincidence/discidence signals. A carrier or a borrow signal is outputted depending whether the number of coincidence signals are more or less than the discidence signal (5). A set output of an FF7 is inputted to the 1st shift register 8 with this signal and a gate circuit is closed after one second and the input signal to a recorder 11 is lost. The recorder 11 is stopped after further 3 seconds with the output of the 2nd shift register 9. The recorder 11 is started with the borrow signal of the counter 6.


Inventors:
YURUGI MASAYOSHI
Application Number:
JP13610981A
Publication Date:
March 10, 1983
Filing Date:
September 01, 1981
Export Citation:
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Assignee:
OKI ELECTRIC IND CO LTD
International Classes:
G11B15/02; G11B5/09; G11B31/00; H04S1/00; (IPC1-7): G11B5/09; G11B15/02; H04S1/00
Attorney, Agent or Firm:
Toshiaki Suzuki