Title:
INFORMATION CACHING CIRCUIT AND METHOD
Document Type and Number:
Japanese Patent JP3169155
Kind Code:
B2
Abstract:
PURPOSE: To provide an information caching circuit and method.
CONSTITUTION: Plural 1st memory positions store the information, and each of these memory positions consists of plural classes and every class includes plural 1st memory positions. Then plural 2nd memory positions store the information acquired from the 1st memory positions. Plural directory positions store the information on the 1st and 2nd memory positions. Every directory position can relate the 2nd memory positions to any of 1st memory positions included in plural classes.
Inventors:
Mark Alan Auslander
Albert Chan
Robert Morris Mead
Albert Chan
Robert Morris Mead
Application Number:
JP23573194A
Publication Date:
May 21, 2001
Filing Date:
September 29, 1994
Export Citation:
Assignee:
International Business Machines Corporation
International Classes:
G06F12/08; (IPC1-7): G06F12/08
Domestic Patent References:
| JP3256148A | ||||
| JP4209049A |
Other References:
情報処理学会編「情報処理ハンドブック」（１９８９−５−３０）オーム社 ｐｐ．２５６−２６０，５３７−５３８
Attorney, Agent or Firm:
Hiroshi Sakaguchi (1 person outside)