Title:
SCANNING CIRCUIT AND SCANNING SIGNAL GENERATING METHOD
Document Type and Number:
Japanese Patent JP3893844
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide a scanning circuit and a scanning signal generating method capable of preventing the generation of a malfunction in a period when the positive/negative logic between clock signals is not realized.
SOLUTION: A scanning circuit is constricted by connecting holding circuits 16, 26, 36, etc., in series. In this case, the holding circuit 16, 36, etc., have the same constitution and the holding circuits 26, 46, etc., have the same constitution. Then, a pulse signal PWM1 which rises at the point of time when a clock pulse &phiv rises and whose width is narrow is impressed on the holding circuits 16, 36, etc., and also a pulse PWM2 which rises at the point of time when the clock pulse &phiv falls and whose width is narrow is impressed on the holding circuits 26, 46, etc. Then, a normal driving signal is made to be forcibly generated by the pulse signals PWM1 and PWM2 at timing when the malfunction is generated and even when the malfunction is generated, the circuit is made so as to perform a normal operation apparently.
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Inventors:
Shin Fujita
Application Number:
JP2000103843A
Publication Date:
March 14, 2007
Filing Date:
April 05, 2000
Export Citation:
Assignee:
Seiko Epson Corporation
International Classes:
G02F1/133; G09G3/36; G09G3/20; (IPC1-7): G09G3/36; G02F1/133; G09G3/20
Domestic Patent References:
| JP6177749A | ||||
| JP10039823A | ||||
| JP2000035773A | ||||
| JP11282397A | ||||
| JP6252723A |
Attorney, Agent or Firm:
Masahiko Ueyanagi
Osamu Suzawa
Osamu Suzawa
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