Title:
SEMICONDUCTOR APPARATUS AND ITS MANUFACTURING METHOD
Document Type and Number:
Japanese Patent JP2007260866
Kind Code:
A
Abstract:
To highly integrate and thin a semiconductor system even when it is furnished with an MEMS device and a semiconductor device.
The semiconductor system is furnished with: a connecting chip having a first chip in which the MEMS device 2a is formed; a second chip 4 in which the semiconductor device 4a is formed; and an adhesive layer 10 to bond a side surface of the first chip and a side surface of the second chip on each other and having a Young's modulus smaller than a material of the first and second chips.
COPYRIGHT: (C)2008,JPO&INPIT
Inventors:
ONOZUKA YUTAKA
YAMADA HIROSHI
FUNAKI HIDEYUKI
ITAYA KAZUHIKO
YAMADA HIROSHI
FUNAKI HIDEYUKI
ITAYA KAZUHIKO
Application Number:
JP2006091242A
Publication Date:
October 11, 2007
Filing Date:
March 29, 2006
Export Citation:
Assignee:
TOSHIBA CORP
International Classes:
B81B7/02; B81C1/00; H01L25/04; H01L25/18
Domestic Patent References:
| JPS5940553A | 1984-03-06 | |||
| JPH02189961A | 1990-07-25 | |||
| JPH0783707A | 1995-03-31 | |||
| JPH09172137A | 1997-06-30 | |||
| JP2003084008A | 2003-03-19 | |||
| JPH05267559A | 1993-10-15 | |||
| JP2002353398A | 2002-12-06 | |||
| JP2001332654A | 2001-11-30 | |||
| JPH077134A | 1995-01-10 | |||
| JP2004014629A | 2004-01-15 |
Foreign References:
| US20050087356A1 | 2005-04-28 |
Attorney, Agent or Firm:
Kenji Yoshitake
Hidetoshi Tachibana
Yasukazu Sato
Hiroshi Yoshimoto
Yasushi Kawasaki
Hidetoshi Tachibana
Yasukazu Sato
Hiroshi Yoshimoto
Yasushi Kawasaki
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