Title:
半導体装置および復号化方法
Document Type and Number:
Japanese Patent JP7390983
Kind Code:
B2
Abstract:
The present invention is to reduce detection of an erroneous edge caused by variation in a case of a sampling frequency that is not larger than a data transmission frequency. A semiconductor device includes: a data reception circuit configured to receive first data at first time and receive second data at second time; and an edge recognition circuit configured to set a range and detect an edge contained in the range. The edge recognition circuit includes a measurement circuit configured to measure a first period taken from the reception of the first data to the reception of the second data, and is configured to determine the range in which the edge contained in the data that is received by the data reception circuit is detected, on the basis of the first period.
Inventors:
Koichi Iwami
Keno Fujii
Keno Fujii
Application Number:
JP2020096553A
Publication Date:
December 04, 2023
Filing Date:
June 03, 2020
Export Citation:
Assignee:
Renesas Electronics Corporation
International Classes:
H04L25/49; H03M5/04; H04L7/04; H04L25/38
Domestic Patent References:
| JP2006157221A | ||||
| JP2014103552A | ||||
| JP2011061525A | ||||
| JP8139711A |
Foreign References:
| US6873642 |
Attorney, Agent or Firm:
Polaire Patent Attorneys Corporation