SEMICONDUCTOR DEVICE AND ITS MANUFACTURING METHOD

Japanese Patent JP3722809

B2

PROBLEM TO BE SOLVED: To prevent polishing waste from entering from the periphery of a wafer when the polishing waste is generated in a rear-face polishing step of the wafer.
SOLUTION: After a buffer coating film 208 is applied onto a wafer, with which a semiconductor device, a multilevel wiring layer, a bonding pad 204, a passivation film 206 and the like are formed, the buffer coating film 208 is patterned by exposure and development, and a part of the buffer coating film 208 located on the bonding pad 204, a scribe line region 210, and an outer peripheral part 218 is removed to form an opening part 208a. While a surface protective tape 212 is stuck on the surface of the wafer 202 with a bonding paste 220, the rear face of the wafer is polished with a polishing solution. As for the outer peripheral part 218, the opening part 208a including the scribe line region 210 is blocked with the adhesive paste 220, and the polishing solution does not permeated.

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Seo Akatsuki
Takayuki Matsuda
Takahiro Nande

JP2003150394A

November 30, 2005

May 28, 2003

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Matsushita Electric Industrial Co., Ltd

H01L21/304; (IPC1-7): H01L21/304

JP2001223210A
JP5315304A
JP2001274129A
JP2137227A

Hiroshi Maeda
Hiroshi Koyama
Hiroshi Takeuchi
Takahisa Shimada
Yuji Takeuchi
Katsumi Imae
Atsushi Fujita
Kazunari Ninomiya
Tomoo Harada
Takashi Goto
Iseki Katsumori

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