Title:
SEMICONDUCTOR DEVICE AND ITS MANUFACTURING METHOD
Document Type and Number:
Japanese Patent JP3923379
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide a semiconductor device and its manufacturing method, capable of keeping a height of a wire loop of low.
SOLUTION: This structure comprises a semiconductor chip 2 mounted to a die pad 1; a lead terminal 6 for connecting this semiconductor chip 2 with an external circuit; a wire 7 of which one end is connected to a pad 4 of the semiconductor chip 2, another end is connected to the lead terminal 6, and a middle part is turned back on an opposite side of the lead terminal of the pad 4; the pad 4; and a sealing resin 8 for sealing a part of the lead terminal 6 and the wire 7.
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Inventors:
Kazuko Narutaki
Application Number:
JP2002182099A
Publication Date:
May 30, 2007
Filing Date:
June 21, 2002
Export Citation:
Assignee:
Renesas Technology Corp.
International Classes:
H01L21/60; (IPC1-7): H01L21/60
Domestic Patent References:
| JP5067643A |
Attorney, Agent or Firm:
Mamoru Takada
Hideki Takahashi
Atsuko Oaku
Atsushi Hirayama
Tamaki Otsuka
Hideki Takahashi
Atsuko Oaku
Atsushi Hirayama
Tamaki Otsuka
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