Title:
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME
Document Type and Number:
Japanese Patent JP2018107230
Kind Code:
A
Abstract:
PROBLEM TO BE SOLVED: To provide an MIS field effect transistor which has a surrounding gate electrode with an SOI structure.SOLUTION: A semiconductor device including an MIS field effect transistor provided on a semiconductor substrate 1 via an insulation film 2 comprises: a fully depleted semiconductor layer as an SOI substrate composed of a structure where a pair of second semiconductor layers 7 are provided to sandwich a third semiconductor layer 8 from both sides and a pair of first semiconductor layers 6 are provided to sandwich the pair of second semiconductor layers 7 from outside; a surrounding gate electrode 10 provided around the third semiconductor layer 8 via a gate oxide film 9; high-concentration source/drain regions (11, 14) which are provided in the first semiconductor layer 6 and have ends having a plane perpendicular to a principal surface of the semiconductor substrate 1; and low-concentration source/drain regions (12, 13) which are provided in the second semiconductor layer 7 and have ends having a plane perpendicular to the principal surface of the semiconductor substrate 1, in which a channel region with channel lengths equal to each other around an entire circumference is provided in the third semiconductor layer 8.SELECTED DRAWING: Figure 1
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Inventors:
SHIRATO TAKEHIDE
Application Number:
JP2016250594A
Publication Date:
July 05, 2018
Filing Date:
December 26, 2016
Export Citation:
Assignee:
SHIRADO TAKEHIDE
International Classes:
H01L29/786; H01L21/336; H01L21/76; H01L21/762; H01L29/41; H01L29/423; H01L29/49