SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME

Japanese Patent JP2018107231

A

PROBLEM TO BE SOLVED: To provide a laminated CMOS having the same channel length around an entire circumference and an integrated surrounding gate electrode.SOLUTION: A CMOS comprises: lower semiconductor layers (11, 12) provided on a semiconductor substrate 1 via interlayer insulation films (2-4); upper semiconductor layers (15-17) provided via laminated interlayer insulation films 6; and an integrated surrounding gate electrode 23 provided around an entire circumference of part (12, 17) of the lower and upper semiconductor layers with a structure to surround the entire circumference via a gate insulation film 22, in which P channel and N channel MIS field effect transistors has a laminated structure composed of one conductivity type source/drain regions (13, 14) with one end being opposite to the part 11 of the lower semiconductor layers and forming a plane perpendicular to a principal surface of the semiconductor substrate in a self-aligned manner with the integrated surrounding gate electrode 23, and opposite conductivity type source/drain regions (18-21) with an end being opposite to the part (15, 16) of the upper semiconductor layers and forming a plane perpendicular to the principal surface of the semiconductor substrate in a self-aligned manner with the integrated surrounding gate electrode 23.SELECTED DRAWING: Figure 1

SHIRATO TAKEHIDE

JP2016250595A

July 05, 2018

December 26, 2016

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SHIRADO TAKEHIDE

H01L29/786; H01L21/20; H01L21/336; H01L21/822; H01L21/8234; H01L21/8238; H01L27/04; H01L27/088; H01L27/092

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