Title:
SEMICONDUCTOR DEVICE, AND MANUFACTURING METHOD THEREOF
Document Type and Number:
Japanese Patent JP3912223
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide a low-cost semiconductor device and the manufacturing method thereof which relaxes the restrictions related to the shapes of its mounted semiconductor chips, etc., with respect to a stacked package wherein a plurality of semiconductor chips are mounted on a wiring board in a laminated manner and in a face-up state, and the wire-bonding electrode pattern portions of the insulating board and the wire-bonding electrode patterns of the semiconductor chips are connected respectively by wire bondings.
SOLUTION: In the stacked package, the thickness of an insulating bonding layer whereby semiconductor chips are bonded to each other is made not smaller than at least the height ranging from the surface of a lower-side semiconductor chip to the uppermost point of the wire loop of its bonding wire. That is, the region present above the surface of the lower-side semiconductor chip which is occupied by the insulating bonding layer is so formed as to overlap at least partially with the wire-bonding electrode region of the lower-side semiconductor chip and that its bonding wire is integrated into the insulating bonding layer.
Inventors:
Kinichi Kumagai
Mitsuhisa Watanabe
Akira Takashima
Mitsuhisa Watanabe
Akira Takashima
Application Number:
JP2002232452A
Publication Date:
May 09, 2007
Filing Date:
August 09, 2002
Export Citation:
Assignee:
富士通株式会社
International Classes:
H01L25/065; H01L25/18; H01L21/52; H01L25/07; (IPC1-7): H01L25/065; H01L21/52; H01L25/07; H01L25/18
Domestic Patent References:
| JP2001308262A | ||||
| JP2002222913A | ||||
| JP10027880A | ||||
| JP8088316A | ||||
| JP62126661A | ||||
| JP2002203939A | ||||
| JP7297311A | ||||
| JP2000269407A |
Attorney, Agent or Firm:
Junichi Yokoyama