Title:
SEMICONDUCTOR DEVICE MANUFACTURING METHOD
Document Type and Number:
Japanese Patent JP2010114250
Kind Code:
A
Abstract:
To prevent variations in dimensions between wirings of a field limiting ring (FLR) pattern, which is caused by residual Poly-Si films upon etching on the side surface of the FLR arranged for the purpose of increasing the breakdown voltage of a Power MOSFET, and to prevent deficiencies of VDSS breakdown voltage characteristics caused by variations of differences in dimensions, thereby improving a yield.
When a gate electrode 8G is formed, Poly-Si films on a semiconductor substrate 3 are processed by dry etching. At that time, SF6 gas is added for etching in addition to Cl2 and O2 used for etching gas to make isotropic etching possible, and thereby an amount of etching residues 9 left on the side surface of an FLR 5 can be reduced.
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Inventors:
OKABE HITOSHI
HARAISHI YOSHIYUKI
HARAISHI YOSHIYUKI
Application Number:
JP2008285311A
Publication Date:
May 20, 2010
Filing Date:
November 06, 2008
Export Citation:
Assignee:
RENESAS TECH CORP
International Classes:
H01L21/336; H01L21/3065; H01L29/06; H01L29/78
Attorney, Agent or Firm:
Yamato Tsutsui